| F | E | G/Memory | Mnemonic | deſcription |
|---|---|---|---|---|
| 00 | 00 | ---- | ERR | Error ſtop |
| 00 | 0x | ---- | NOP | |
| 77 | 00 | ---- | HLT | |
| 77 | 77 | ---- | HLT | |
| 01 | 01 | ---- | PTA | P → A |
| 01 | 02 | ---- | LS1 | Shift left |
| 01 | 03 | ---- | LS2 | Shift left ⨯2 |
| 01 | 04 | ---- | CBC | Clear Buffer Controls |
| 01 | 05 | xxxx | ATE | A → BER |
| 01 | 06 | xxxx | ATX | A → BXR |
| 01 | 07 | ---- | ETA | BER → A |
| 01 | 10 | ---- | SL3 | Shift Left ⨯3 |
| 01 | 11 | ---- | SL6 | Shift Left ⨯6 |
| 01 | 12 | ---- | MUT | A ⨯ 10 → A |
| 01 | 13 | ---- | MUH | A ⨯ 100 → A |
| 01 | 14 | ---- | RS1 | Shift Right |
| 01 | 15 | ---- | RS2 | Shift Right ⨯2 |
| 01 | 20 | ---- | CIL | Clear Interrupt Lockout. |
| 01 | 30 | ---- | CTA | Bank Controls → A |
| 01 | 4x | ---- | SBU | Set Buffer Bank Control |
| 01 | 5x | ---- | STP | ſtore P in loc. 5x |
| 01 | 6x | ---- | STE | ſtore BER in loc. 6x ⋄ A → BER |
| 01 | 00 | 0000 | ||
| 01 | 00 | 0000 |